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IEEE ICASSP 2022 || Singapore || 7-13 May 2022 Virtual; 22-27 May 2022 In-Person

IEEE ICASSP 2022

2022 IEEE International Conference on Acoustics, Speech and Signal Processing

7-13 May 2022
  • Virtual (all paper presentations)
22-27 May 2022
  • Main Venue: Marina Bay Sands Expo & Convention Center, Singapore
27-28 October 2022
  • Satellite Venue: Crowne Plaza Shenzhen Longgang City Centre, Shenzhen, China

ICASSP 2022
ST-18: Hardware Demonstration of Low-rate and High-Dynamic Range ADC
Fri, 13 May, 23:00 - 23:45 China Time (UTC +8)
Fri, 13 May, 15:00 - 15:45 UTC
Location: Gather Area P
Virtual
Gather.Town
Show & Tell
Presented by: 1. Satish Mulleti, Department of Electrical Engineering, Indian Institute of Technology (IIT) Bombay 2. Eyar Azar, The Weizmann Institute of Science 3. Shaik Basheeruddin Shah, The Weizmann Institute of Science 4. Nimrod Glazer, The Weizmann Institute of Science 5. Shlomi Savariego, The Weizmann Institute of Science 6. Oded Cohen, The Weizmann Institute of Science 7. Eliya Reznitskiy, The Weizmann Institute of Science 8. Moshe Namer, The Weizmann Institute of Science 9. Yonina C. Eldar, The Weizmann Institute of Science

In this demo, we present a low-rate, high-dynamic-range analog to digital conversion (ADC).

While sampling signals through an ADC, typically, it is assumed that the signal’s dynamic range is within the dynamic range of the ADC. However, in many applications, such as radar and ultrasound imaging, the dynamic range of the received signal could be beyond that of the ADC which results in clipping and leads to inaccurate reconstruction. A modulo preprocessing can be used to avoid clipping and sampling signals beyond the dynamic range of the ADC [1]. The modulo step folds the signal to the dynamic range of the ADC, and the folded signal is sampled. During reconstruction, the true samples are recovered from the folded ones by using an unfolding algorithm. Typically, the unfolding algorithms operate at a much higher rate compared to the rate without a modulo operation. This results in a large number of bits per second (NMBPS) post sampling and quantization which may not be suitable in many applications as a large amount of storage or transmission bandwidth is required.

In his demo, we propose modulo hardware that produces side information in addition to performing the folding operation. Specifically, the hardware gathers the information of the folding instants. It is well known that if the folded samples and the folding instants are given then the algorithm does not require a large sampling rate. However, this requires storage or transmission of quantized values of folded samples and the folding instants which again increases the NMBPS. To keep the NMBPS small, the proposed hardware distributes the information of the folding instants across all the samples such that each folded sample is padded with a few additional bits. In this way, the overall NMBPS is much lower than the methods where the side information is not stored.

References: [1] A. Bhandari, F. Krahmer and R. Raskar, "On Unlimited Sampling and Reconstruction," in IEEE Transactions on Signal Processing, vol. 69, pp. 3827-3839, 2021.