My ICASSP 2017 Schedule
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Paper Detail
| Paper: | DISPS-P1.7 | ||
| Session: | Design and Implementation of Signal Processing Systems II | ||
| Session Time: | Thursday, March 9, 13:30 - 15:30 | ||
| Presentation Time: | Thursday, March 9, 13:30 - 15:30 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Algorithm and architecture co-optimization | ||
| Paper Title: | MULTIPLE PARALLEL BRANCH WITH FOLDING ARCHITECTURE FOR MULTICHANNEL FILTERED-X LEAST MEAN SQUARE ALGORITHM | ||
| Authors: | Dongyuan Shi; Nanyan Technology University | ||
| Jianjun He; Nanyan Technology University | |||
| Chuang Shi; Nanyan Technology University | |||
| Tatsuya Murao; Nanyan Technology University | |||
| Woon-Seng Gan; Nanyan Technology University | |||