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My ICASSP 2017 Schedule

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Paper Detail

Session:Design and Implementation of Signal Processing Systems II
Session Time:Thursday, March 9, 13:30 - 15:30
Presentation Time:Thursday, March 9, 13:30 - 15:30
Presentation: Poster
Topic: Design and Implementation of Signal Processing Systems: DSP algorithm implementation in hardware and software
Paper Title: Constrain the Docile CTUs: an In-Frame Complexity Allocator for HEVC Intra Encoders
Authors: Alexandre Mercat; IETR 
 Florian Arrestier; IETR 
 Wassim Hamidouche; IETR 
 Maxime Pelcat; IETR 
 Daniel Menard; IETR