Tutorial 6: Clocking and Synchronization issues in sub-100nm System on Chip (SoC) Designs


Ramalingam Sridhar; State University of New York at Buffalo
Ram Krishnamurthy; Intel Corporation
Sanu K. Mathew; Intel Corporation

Time & Location

Sunday Afternoon, May 23, 13:15 - 16:15, Location: Junior Ballroom A


The idea of combining high-speed digital cores, memory arrays, analog blocks and communication circuitry onto a single chip has generated much interest and led to a whole new design era of System on Chips (SoC). As a result, several new and important applications that integrate systems from diverse resources are seen in the market today.

The structure of deep submicron interconnects, that form the clock distribution network, and the proximity between interconnection wires lead to capacitive and inductive coupling between them. Apart from increasing the wire delays, this cross-coupling between wires induces unpredictability in wire delay. Due to this, the timing plan of the system is easily upset and may lead to malfunctioning of the entire system. The sensitivity of wire delay to environmental and process variations is also considerably higher in Ultra DSM circuits. With these wires forming the clock distribution network, the delay, skew and integrity of the clock signals is affected, leading to failure of synchronization between the various components on chip. In this tutorial, we will discuss the importance of these issues and how they affect the clocking and synchronization in SoCs.

One of the important features of this type of design is integration into smaller chip area, which also yields favorable characteristics such as low power dissipation and is well suited for sophisticated applications. However, the increasing density of devices on chip leads to a new set of problems, caused by very high power densities. Leakage power contributes to a significant portion of power consumed in DSM circuits. Hence techniques that aim at reducing clock power consumption and clock skew in deep submicron circuits are addressed. Clock distribution network is another important component of the SoC, which consumes a significant portion of the total power. Techniques that reduce clock skew and maintain clock signal integrity will be presented. This includes, design of the clock distribution networks, partitioning of clock regions and resynchronization of data as it passes through different clock domains. Globally Asynchronous Locally Synchronous (GALS) designs and multiphase clock generation will be discussed.

Techniques that are used to design SoCs in the presence of the various sources of delay unpredictability are presented with practical examples. Pointers towards techniques that will allow design of SoCs which do not compromise on performance and still optimally use the resources available are also presented. High frequency data path circuit designs in UDSM domain will be detailed.

Presenter Information

Ramalingam Sridhar is with the Department of Computer Science & Engineering at University of Buffalo, (SUNY). His research interests are in Deep submicron VLSI Design, Wave Pipelining, Clocking and Synchronization, Low power DSP and memories, high level power minimization and embedded system designs. He got his Ph.D. in Electrical and Computer Engineering from Washington State University, Pullman, Washington. He has served/serving on the editorial board of IEEE Transactions on VLSI System, IEEE Transactions on Circuits and Systems I & II, IEEE Circuits and Devices magazine and Journal of Circuits, Systems and Computers. He was Program Chair, General Chair and Steering Committee Chair of IEEE ASIC/SoC Conference and has been on numerous conference technical committees. Dr. Sridhar has several patents and publications in his research areas. He was selected as the Teacher of the Year in Engineering by Tau Beta Pi and was awarded a Lilly Teaching Fellowship.

Ram K. Krishnamurthy received the B.E. degree in Electrical Engineering from Regional Engineering College, Trichy, India, in 1993, and the Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh, PA, in 1998. Since graduation, he has been with Intel’s Microprocessor Research Labs in Hillsboro, Oregon, where he is currently a Senior Staff Engineer and Manager of the high-performance and low-voltage circuits research group. He is an adjunct faculty of Electrical and Computer Engineering, Oregon State University. His current research interests are in high-performance and low-power datapath, DSP, and interconnect design.

He holds 28 patents, 40 pending, and has published over 50 papers in refereed journals and conferences. Krishnamurthy serves as Intel´s representative on SRC ICSS Design Sciences Task Force and on many conference program committees. He is the Technical Program Co-Chair for the 2003 IEEE International SoC Conference. Krishnamurthy has received numerous awards for his service and research.

Sanu Mathew is with circuit research, Intel Labs, Intel Corporation, Hillsboro, OR. He received his Ph.D. degree in Electrical and Computer Engieneering from The State University of New York at Buffalo, Buffalo, NY in 1999. His research interests include high performance low power circuits; datapath architectures, leakage-tolerant techniques, on-chip memory structures, interconnect interfaces, and clock generation methods.

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