Technical Program

Paper Detail

Paper:COMM-P2.5
Session:Communication Circuits Design I
Time:Monday, May 24, 11:15 - 12:45
Presentation: Poster
Topic: Circuits and Systems for Communications: Wireless Communications Circuits
Title: IMPROVING THE ACQUISITION TIME OF A PLL-BASED, INTEGER-N FREQUENCY SYNTHESIZER
Authors: Syed Irfan Ahmed; Carleton University 
 Ralph Mason; Carleton University 
Abstract: A Phase-Locked Loop-based frequency synthesizer switches between channels as the feedback division ratio is changed. For a given spectral purity, the acquisition time is often the bottleneck in the design of integer-N synthesizers. This paper presents a review of the three major phases of the total acquisition time from control systems theory and PLL literature. These are the pull-in time, the settling-time and the lock-time. An implementation example in 0.25um CMOS process illustrates the process of reduction of the acquisition time by a factor of 3.5 for an integer-N synthesizer.
 
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