Technical Program

Paper Detail

Paper:CAD-L7.5
Session:Interconnect and Clock Distribution
Time:Tuesday, May 25, 15:27 - 15:45
Presentation: Lecture
Topic: Computer-Aided Network Design: Interconnect and Clock Distribution
Title: DELAY BOUND BASED CMOS GATE SIZING TECHNIQUE
Authors: Philippe Maurine; Université de Montpellier II 
 Xavier Michel; Université de Montpellier II 
 Alexandre Verle; Université de Montpellier II 
 Nadine Azémard; Université de Montpellier II 
 Daniel Auvergne; Université de Montpellier II 
Abstract: In this paper we address the problem of delay constraint distribution on a CMOS combinatorial path. We first define a way to determine on any path the reasonable bounds of delay characterizing the structure. Then we define two constraint distribution methods that we compare to the equal delay distribution and to an industrial tool based on Newton-Raphson like algorithms. Validation is obtained on a 0.25?m process by comparing the different constraint distribution techniques on various benchmarks.).
 
           Back


Home -||- Technical Program -||- Call for Participation -||- Paper Submission -||- Paper Review -||- Plenaries
Invited Sessions -||- Registration -||- Tutorials/Short Courses -||- Forums -||- Technical Program Committee
MySchedule -||- Exhibits -||- Housing -||- Information -||- Committee -||- Contact Us

©2021 Conference Management Services -||- email: organizers@iscas2004.org -||- Last updated Friday, August 17, 2012