Technical Program

Paper Detail

Paper:COMM-P5.5
Session:Computation Kernels and IP for Communication Systems II
Time:Tuesday, May 25, 14:15 - 15:45
Presentation: Poster
Topic: Circuits and Systems for Communications: Wireline Communications Circuits (Gigabit Ethernet, SONET, other wireline)
Title: JITTER IN HIGH-SPEED SERIAL AND PARALLEL LINKS
Authors: Pavan Kumar Hanumolu; Oregon State University 
 Un-Ku Moon; Oregon State University 
 Gu-Yeon Wei; Harvard University 
 Randy Mooney; Intel Corporation 
 Bryan Casper; Intel Corporation 
Abstract: Jitter degrades the performance of both high-speed serial and parallel I/O links by limiting the maximum achievable data-rates. We present analytical expressions to evaluate the effect of jitter on the performance of high-speed links. These expressions enable simple calculation of worst-case voltage and timing margins in the presence of jitter. This analysis is also extended to equalized links. Finally, we show that the limited bandwidth of the channel can amplify high frequency jitter and present means to counteract jitter amplification.
 
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