Technical Program

Paper Detail

Paper:VLSI-L16.2
Session:Cryptography
Time:Tuesday, May 25, 16:18 - 16:36
Presentation: Lecture
Topic: VLSI Systems and Applications: VLSI Programmable, Reconfigurable, and Array Architecture
Title: DESIGN OF A RECONFIGURABLE AES ENCRYPTION/DECRYPTION ENGINE FOR MOBILE TERMINALS
Authors: Thilo Pionteck; Darmstadt University of Technology 
 Thorsten Staake; Darmstadt University of Technology 
 Thomas Stiefmeier; Darmstadt University of Technology 
 Lukusa D. Kabulepa; Darmstadt University of Technology 
 Manfred Glesner; Darmstadt University of Technology 
Abstract: This work presents the hardware design of a reconfigurable encryption/decryption engine for the Advanced Encryption Standard (AES) supporting all key lengths. The reconfigurable crypto-engine is integrated as a function unit in a 32 bit RISC processor and can operate in parallel with the standard ALU. Neither the pipeline structure nor the control logic for register forwarding and hazard detection are affected, allowing an easy integration into different RISC architectures. Reconfiguration can be done during runtime, allowing the processor to utilize the arithmetic components and memory elements of the crypto-unit for additional tasks like multiplication in the Galois Field GF(2^8) required for Reed-Solomon code generation. The RISC processor with the crypto-engine was synthesized using a 0.25 µm CMOS technology.
 
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