Paper: | CAD-L7.1 | ||

Session: | Interconnect and Clock Distribution | ||

Time: | Tuesday, May 25, 14:15 - 14:33 | ||

Presentation: | Lecture | ||

Topic: | Computer-Aided Network Design: Interconnect and Clock Distribution | ||

Title: | PARTIAL RANDOM WALK FOR LARGE LINEAR NETWORK ANALYSIS | ||

Authors: | Weikun Guo; University of California, Riverside | ||

Sheldon Tan; University of California, Riverside | |||

Zuying Luo; Tsinghua University | |||

Xianlong Hong; Tsinghua University | |||

Abstract: | This paper proposes a new simulation algorithm for analyzing large power distribution networks, modeled as linear RLC circuits, based on a novel partial random walk concept. The random walk simulation method has been shown to be an efficient way to solve for a small number of nodes in a lager power distribution network [6], but the algorithm becomes expensive to solve for nodes that are more than a few. In this paper, we combine direct methods like LU factorization with the random walk concept to solve power distribution networks when a significant number of node waveforms is required. We also apply an equivalent circuit modeling method to speed up the direct simulation of subcircuits. Experimental results show that the resulting algorithm, called partial random walk (PRW), has significant advantages over the pure random walk method especially when the VDD/GND nodes are sparse and accuracy requirement is high. | ||

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