Technical Program

Paper Detail

Paper:ASP-P21.4
Session:Sigma-Delta Converters IV
Time:Wednesday, May 26, 11:15 - 12:45
Presentation: Poster
Topic: Analog Signal Processing: Data Converters, Sigma Delta, A/D, D/A, other Data Converters
Title: A 4TH ORDER SINGLE-LOOP DELTA-SIGMA ADC WITH 8-BIT TWO-STEP FLASH QUANTIZATION
Authors: Yongjie Cheng; Brigham Young University 
 Craig Petrie; Brigham Young University 
 Brent Nordick; Brigham Young University 
Abstract: An architecture for a multibit single-loop delta-sigma A/D converter with two-step internal quantization is presented. Both the MSB and LSB signals produced by the two-step quantization are fed back simultaneously to all integrator stages. Thus the problem of inter-stage quantization noise leakage, which limits the performance of cascaded delta-sigma architectures, is avoided. Several architectural enhancements that facilitate a large number of quantizer levels within a single-loop modulator are presented. Behavioral simulation results demonstrate that for a 4th-order, 8-bit modulator, 108 dB of signal-to-quantization noise is achievable at an oversampling ratio of 8.
 
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