Technical Program

Paper Detail

Paper:DSP-L3.1
Session:Digital Filters
Time:Monday, May 24, 14:15 - 14:33
Presentation: Lecture
Topic: Digital Signal Processing: Digital Filter Design and Implementation
Title: FPGA-BASED 3D MEDIAN FILTERING USING WORD-PARALLEL SYSTOLIC ARRAYS
Authors: Carlos Castro-Pareja; The Ohio State University 
 Jogikal Jagadeesh; The Ohio State University 
 Sharmila Venugopal; The Ohio State University 
 Raj Shekhar; The Cleveland Clinic Foundation 
Abstract: A 3D median filter architecture suitable for FPGA implementation is presented. The architecture consists of an ordered semi-systolic array of size equal to the filter window size. The hardware requirements of the architecture are significantly lower than those of previously reported systolic array architectures, making it desirable for the implementation of filters with large kernel sizes. An implementation of a 3x3x3 filter in an Altera EP1C3T100C6 FPGA achieved a clock rate in excess of 100 MHz, being able to process a 128x128x128 image in 0.2 seconds. An implementation of a 3x3 2D filter achieved a clock rate in excess of 130MHz.
 
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