VLSI-P5: VLSI Architectures

Session Type: Poster
Time: Tuesday, May 25, 09:30 - 11:00
Location: Poster Area 9
Chair: Jerry Jou, National Central University, Taiwan
 
VLSI-P5.1: REDUCED BINARY TREE FIR FILTERS
         Artur Wr√≥blewski; Munich University of Technology
         Marek Wr√≥blewski; Munich University of Technology
         Christoph Saas; Munich University of Technology
         Josef A. Nossek; Munich University of Technology
 
VLSI-P5.2: PHASED TAG CACHE: AN EFFICIENT LOW POWER CACHE SYSTEM
         Rui Min; University of Cincinnati
         Wenben Jone; University of Cincinnati
         Yiming Hu; University of Cincinnati
 
VLSI-P5.3: MICROSYSTEM CONTROLLER FOR SENSOR NETWORK CONTROL AND DATA CORRECTION
         Prasanna Balasundaram; Michigan State University
         Kartik Vaidyanathan; Michigan State University
         Andrew Mason; Michigan State University
 
VLSI-P5.4: A DYNAMIC TASK SCHEDULING ALGORITHM FOR BATTERY POWERED DVS SYSTEMS
         Jameel Ahmed; Arizona State University
         Chaitali Chakrabarti; Arizona State University
 

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