VLSI-P2: Low Power Design and Implementation II

Session Type: Poster
Time: Monday, May 24, 11:15 - 12:45
Location: Poster Area 10
Chair: Mark Barry, Silicon & Software Systems
 
VLSI-P2.1: HIGH PERFORMANCE SENSE AMPLIFIER CIRCUIT FOR LOW POWER SRAM APPLICATIONS
         Hwang-Cherng Chow; Chang Gung University
         Shu-Hsien Chang; Chang Gung University
 
VLSI-P2.2: EVALUATION OF POWER CUT-OFF TECHNIQUES IN THE PRESENCE OF GATE LEAKAGE
         Mindaugas Draždžiulis; Chalmers University of Technology
         Per Larsson-Edefors; Chalmers University of Technology
 
VLSI-P2.3: CROSSTALK ENERGY REDUCTION BY TEMPORAL SHIELDING
         Sabino Salerno; Politecnico di Torino
         Enrico Macii; Politecnico di Torino
         Massimo Poncino; Università di Verona
 
VLSI-P2.4: A POWER-OPTIMIZED 64-BIT PRIORITY ENCODER UTILIZING PARALLEL PRIORITY LOOK-AHEAD
         Cheong Kun; Michigan State University
         Shaolei Quan; Michigan State University
         Andrew Mason; Michigan State University
 
VLSI-P2.5: A MAXIMUM TOTAL LEAKAGE CURRENT ESTIMATION METHOD
         Yongjun Xu; Chinese Academy of Sciences
         Zuying Luo; Tsinghua University
         Xiaowei Li; Chinese Academy of Sciences
 

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