DSP-P8: Digital Signal Processing IV

Session Type: Poster
Time: Tuesday, May 25, 11:15 - 12:45
Location: Poster Area 6
Chair: Zhiping Lin, Nanyang Technological University
 
DSP-P8.1: FPGA ARCHITECTURES FOR REAL-TIME 2D/3D FIR/IIR PLANE WAVE FILTERS
         Arjuna Madanayake; University of Calgary
         Leonard Bruton; University of Calgary
         Chris Comis; University of Calgary
 
DSP-P8.2: ADAPTIVE LMS PROCESSING ARCHITECTURES EMPLOYING FREQUENCY DOMAIN SUB-CONVOLUTION
         Andrew Gray; JPL / California Institute of Technology
         Scott Hoy; NASA / Goddard Space Flight Center
         Parminder Ghuman; NASA / Goddard Space Flight Center
 
DSP-P8.3: A REUSABLE IP FFT CORE FOR DSP APPLICATIONS
         Evaggelia Theochari; Democritus University of Thrace
         Konstantinos Tatas; Democritus University of Thrace
         Dimitrios Soudris; Democritus University of Thrace
         Konstantinos Masselos; Intracom SA, Hellenic Telecommunications Industry
         Konstantinos Potamianos; Intracom SA, Hellenic Telecommunications Industry
         Spyros Blionas; Intracom SA, Hellenic Telecommunications Industry
         Antonios Thanailakis; Democritus University of Thrace
 
DSP-P8.4: VLSI PROCESSOR ARCHITECTURE FOR REAL-TIME GA PROCESSING AND PE-VLSI DESIGN
         Tetsuya Imai; Ritsumeikan University
         Masaya Yoshikawa; Ritsumeikan University
         Hidekazu Terai; Ritsumeikan University
         Hironori Yamauchi; Ritsumeikan University
 
DSP-P8.5: AN EXTENDED GENERALIZED SIDELOBE CANCELLER IN TIME AND FREQUENCY DOMAIN
         Zhu Liang Yu; Nanyang Technological University
         Meng Hwa Er; Nanyang Technological University
 

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