NLCS-P2: Nonlinear Circuits Analysis and Design II

Session Type: Poster
Time: Monday, May 24, 11:15 - 12:45
Location: Poster Area 6
Chair: Takashi Hisikado, University of Kyoto
 
NLCS-P2.1: STABILITY ANALYSIS OF POWER CIRCUIT COMPRISING VIRTUAL INDUCTANCE
         Octavian Dranga; Utsunomiya University
         Hirohito Funato; Utsunomiya University
         Satoshi Ogasawara; Utsunomiya University
         Chi K. Michael Tse; Hong Kong Polytechnic University
         Herbert Iu; University of Western Australia
 
NLCS-P2.2: AN UNLIMITED LOCK RANGE DLL FOR CLOCK GENERATOR
         Kwangoh Kim; Dawintech, Inc.
         Nohman Park; Dawintech, Inc.
         Taekyu Kim; Dawintech, Inc.
 
NLCS-P2.3: DESIGN AND SIMULATION OF FRACTIONAL-N PLL FREQUENCY SYNTHESIZERS
         Mücahit Kozak; University of Rochester
         Eby G. Friedman; University of Rochester
 
NLCS-P2.4: MAINTAINING CHAOS IN AN ASSOCIATIVE CHAOTIC NEURAL NETWORK EXHIBITING INTERMITTENCY
         Masaharu Adachi; Tokyo Denki University
 
NLCS-P2.5: A MIXED PLL/DLL ARCHITECTURE FOR LOW JITTER CLOCK GENERATION
         Yong-Cheol Bae; Harvard University
         Gu-Yeon Wei; Harvard University
 

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