VLSI-P3: Video IP Cores

Session Type: Poster
Time: Tuesday, May 25, 09:30 - 11:00
Location: Poster Area 1
Chair: Jerry Jou, National Central University, Taiwan
 
VLSI-P3.1: ARCHITECTURE DESIGN OF MDCT-BASED PSYCHOACOUSTIC MODEL CO-PROCESSOR IN MPEG ADVANCED AUDIO CODING
         Tsung-Han Tsai; National Central University
         Shih-Way Huang; National Taiwan University
         Yi-Wen Wang; National Central University
 
VLSI-P3.2: A LOW-POWER DCT IP CORE BASED ON 2D ALGEBRAIC INTEGER ENCODING
         Minyi Fu; University of Windsor
         Graham Jullien; University of Calgary
         Vassil Dimitrov; University of Calgary
         Majid Ahmadi; University of Windsor
 
VLSI-P3.3: A PARAMETERIZED POWER-AWARE IP CORE GENERATOR FOR THE 2-D 8X8 DCT/IDCT
         Rei-Chin Ju; National Chung Cheng University
         Jia-Wei Chen; National Chung Cheng University
         Jiun-In Guo; National Chung Cheng University
         Tien-Fu Chen; National Chung Cheng University
 
VLSI-P3.4: VLSI DESIGN OF DUAL-MODE VITERBI/TURBO DECODER FOR 3GPP
         Kai Huang; National Taiwan University
         Fan-Min Li; National Taiwan University
         Pei-Ling Shen; National Taiwan University
         An-Yeu (Andy) Wu; National Taiwan University
 
VLSI-P3.5: A COST-EFFECTIVE MPEG-4 SHAPE-ADAPTIVE DCT WITH AUTO-ALIGNED TRANSPOSE MEMORY ORGANIZATION
         Kun-Bin Lee; National Chiao Tung University
         Hui-Cheng Hsu; National Chiao Tung University
         Chein-Wei Jen; National Chiao Tung University
 

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