VLSI-P10: Image Processing and Implementation

Session Type: Poster
Time: Wednesday, May 26, 09:30 - 11:00
Location: Poster Area 9
Chair: Mircea R. Stan, University of Virginia
 
VLSI-P10.1: AN ARCHITECTURE FOR FRACTAL IMAGE COMPRESSION USING QUAD-TREE MULTIRESOLUTION
         Alejandro Martínez-Ramírez; INAOE
         Alejandro Díaz Sánchez; INAOE
         Mónico Linares-Aranda; Instituto Nacional de Astrofísica, Óptica y Electrónica
         Javier Vega-Pineda; ITCh
 
VLSI-P10.2: ON BOARD PROCESSOR DEVELOPMENT FOR NASA'S SPACEBONE IMAGING RADAR WITH VLSI SYSTEM-ON-CHIP TECHNOLOGY
         Wai-Chi Fang; NASA's Jet Propulsion Laboratory
         Michael Jin; NASA's Jet Propulsion Lab
 
VLSI-P10.3: LOW COST AND LATENCY EMBEDDED 3D GRAPHICS RECIPROCATION
         Dan Crisu; Delft University of Technology
         Stamatis Vassiliadis; Delft University of Technology
         Sorin Cotofana; Delft University of Technology
         Petri Liuha; Nokia Research Center
 
VLSI-P10.4: SYSTOLIC COUNTERS WITH UNIQUE ZERO STATE
         Mircea Stan; University of Virginia
 
VLSI-P10.5: SOBEL EDGE DETECTION PROCESSOR FOR A REAL-TIME VOLUME RENDERING SYSTEM
         Natalia Kazakova; University of Alberta
         Martin Margala; University of Rochester
         Nelson Durdle; University of Alberta
 

Home -||- Technical Program -||- Call for Participation -||- Paper Submission -||- Paper Review -||- Plenaries
Invited Sessions -||- Registration -||- Tutorials/Short Courses -||- Forums -||- Technical Program Committee
MySchedule -||- Exhibits -||- Housing -||- Information -||- Committee -||- Contact Us

©2021 Conference Management Services -||- email: organizers@iscas2004.org -||- Last updated Friday, August 17, 2012