ASP-P17: Data Converters III

Session Type: Poster
Time: Wednesday, May 26, 09:30 - 11:00
Location: Poster Area 6
Chair: Luis Hernandez, University Carlos III
 
ASP-P17.1: MODELLING AND OPTIMIZATION OF LOW PASS CONTINUOUS-TIME SIGMA-DELTA MODULATORS FOR CLOCK JITTER NOISE REDUCTION
         Luis Hernández; Universidad Carlos III de Madrid
         Andreas Wiesbauer; Infineon Technologies AG
         Susana Patón; Universidad Carlos III de Madrid
         Antonio Di Giandomenico; Infineon Technologies AG
 
ASP-P17.2: DESIGN ISSUES AND PERFORMANCE LIMITATIONS OF A CLOCK JITTER INSENSITIVE MULTIBIT DAC ARCHITECTURE FOR HIGH-PERFORMANCE LOW-POWER CT ?? MODULATORS
         Friedel Gerfers; Philips Semiconductors GmbH
         Maurits Ortmanns; Albert-Ludwigs-University Freiburg
         Yiannos Manoli; Albert-Ludwigs-University Freiburg
 
ASP-P17.3: SIGMA-DELTA MODULATORS OPERATED IN OPTIMIZATION MODE
         Shiang-Hwua Yu; National Sun Yat-Sen University
         Jwu-Sheng Hu; National Chiao Tung University
 
ASP-P17.4: REDUCING QUANTIZATION NOISE WITH RECURSIVE SIGMA-DELTA MODULATORS
         Daniël Schinkel; University of Twente
         Ed van Tuijl; University of Twente
         Anne-Johan Annema; University of Twente
 
ASP-P17.5: TAKING ADVANTAGE OF LVDS INPUT BUFFERS TO IMPLEMENT SIGMA-DELTA A/D CONVERTERS IN FPGAS
         Fabio Sousa; Altera Europe
         Volker Mauer; Altera Europe
         Neimar Duarte; PI Componentes / Altera
         Ricardo Jasinski; Federal Center of Technological Education of Paran
         Volnei Pedroni; Federal Center of Technological Education of Paran
 

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