VLSI-L5: Low Power Buses and Circuits

Session Type: Lecture
Time: Monday, May 24, 14:15 - 15:45
Location: Junior Ballroom A/B
Co-Chairs: Ramalingam Sridhar, SUNYat Buffalo and Robert C. Chang, National Chung Hsin University
 
VLSI-L5.1: DYNAMIC RECONFIGURABLE BUS ENCODING SCHEME FOR REDUCING THE ENERGY CONSUMPTION OF DEEP SUB-MICRON INSTRUCTION BUS
         Siu-Kei Wong; Hong Kong University of Science and Technology
         Chi-Ying Tsui; Hong Kong University of Science and Technology
 
VLSI-L5.2: LOW POWER COUPLING-BASED ENCODING FOR ON-CHIP BUSES
         Maged Ghoneima; Northwestern University
         Yehea Ismail; Northwestern University
 
VLSI-L5.3: UNIFIED BUS ENCODING BY STREAM RECONSTRUCTION WITH VARIABLE STRIDES
         Tien-Fu Chen; National Chung Cheng University
         Tsung-Ming Hsieh; National Chung Cheng University
         Chun-Li Wei; National Chung Cheng University
 
VLSI-L5.4: A NEW PARALLEL ARCHITECTURE FOR LOW POWER LINEAR FEEDBACK SHIFT REGISTERS
         Abdullah Mamun; North Dakota State University
         Rajendra Katti; North Dakota State University
 
VLSI-L5.5: A LOW-POWER GROUP-BASED VLD DESIGN
         Cheng-Hung Liu; National Chiao Tung University
         Bai-Jue Shieh; Sunplus Technology Co., Ltd.
         Chen-Yi Lee; National Chiao Tung University
 

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