VLSI-L20: Memory

Session Type: Lecture
Time: Wednesday, May 26, 11:15 - 12:45
Location: Junior Ballroom C
Co-Chairs: Mark Barry, Silicon & Software Systems and Ming-Der Shieh, National Cheng Kung University
 
VLSI-L20.1: A NEW DUAL PUMPING CIRCUIT WITHOUT BODY EFFECTS FOR LOW SUPPLY VOLTAGE
         Ming-chih Hsieh; National Chung Hsing University
         Zheng-hong Wang; National Chung Hsing University
         Hongchin Lin; National Chung Hsing University
         Yen-Tai Lin; eMemory Technology Inc.
 
VLSI-L20.2: A FULLY SYMMETRICAL SENSE AMPLIFIER FOR NON-VOLATILE MEMORIES
         Ferdinando Bedeschi; STMicroelectronics
         Edoardo Bonizzoni; University of Pavia
         Osama Khouri; STMicroelectronics
         Claudio Resta; STMicroelectronics
         Guido Torelli; University of Pavia
 
VLSI-L20.3: STATIC DIVIDED WORD MATCHING LINE FOR LOW-POWER CONTENT ADDRESSABLE MEMORY DESIGN
         Kuo-Hsing Cheng; National Central University
         Chia-Hung Wei; Tamkang University
         Shu-Yu Jiang; National Central University
 
VLSI-L20.4: LOW POWER DUAL MATCHLINE TERNARY CONTENT ADDRESSABLE MEMORY
         Nitin Mohan; University of Waterloo
         Manoj Sachdev; University of Waterloo
 
VLSI-L20.5: EFFICIENT HARDWARE IMPLEMENTATION OF A CRYTO-MEMORY BASED ON AES ALGORITHM AND SRAM ARCHITECTURE
         Anna Labbé; L2MP-Polytech
         Annie Pérez; L2MP-Polytech
         Jean-Michel Portal; L2MP-Polytech
 

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