CAD-L9: Verification, Testing, and Validation

Session Type: Lecture
Time: Wednesday, May 26, 09:30 - 11:00
Location: Galiano
Co-Chairs: Steven Martin, University of Michigan and Sung Kyu Lim, Georgia Institute of Technology
 
CAD-L9.1: A NEW GENERATION OF ISCAS BENCHMARKS FROM FORMAL VERIFICATION OF HIGH-LEVEL MICROPROCESSORS
         Miroslav Velev; Carnegie Mellon University
 
CAD-L9.2: ESDINSPECTOR: A NEW LAYOUT-LEVEL ESD PROTECTION CIRCUITRY DESIGN VERIFICATION TOOL USING A SMART-PARAMETRIC CHECKING MECHANISM
         Rouying Zhan; Illinois Institute of Technology
         Haigang Feng; Illinois Institute of Technology
         Haolu Xie; Illinois Institute of Technology
         Albert Wang; Illinois Institute of Technology
 
CAD-L9.3: FAULT EQUIVALENCE AND DIAGNOSTIC TEST GENERATION USING ATPG
         Andreas Veneris; University of Toronto
         Robert Chang; University of Toronto
         Magdy S. Abadir; Motorola, Inc.
         Mandana Amiri; University of British Columbia
 
CAD-L9.4: A HYBRID-TYPE TEST PATTERN GENERATING MECHANISM
         Chuen-Yau Chen; National Yunlin University of Science and Technology
         An-Chi Hsu; National Yunlin University of Science and Technology
 
CAD-L9.5: PLACEMENT AND ROUTING OPTIMIZATION FOR CIRCUITS DERIVED FROM BDDS
         Thomas Eschbach; Albert-Ludwigs-University
         Rolf Drechsler; University of Bremen
         Bernd Becker; Albert-Ludwigs-University
 

Home -||- Technical Program -||- Call for Participation -||- Paper Submission -||- Paper Review -||- Plenaries
Invited Sessions -||- Registration -||- Tutorials/Short Courses -||- Forums -||- Technical Program Committee
MySchedule -||- Exhibits -||- Housing -||- Information -||- Committee -||- Contact Us

©2021 Conference Management Services -||- email: organizers@iscas2004.org -||- Last updated Friday, August 17, 2012