VLSI-P12: Array Architecture and SoC

Session Type: Poster
Time: Wednesday, May 26, 11:15 - 12:45
Location: Poster Area 9
Chair: Dimitrios Soudris, Democritus University of Trace
 
VLSI-P12.1: VLSI ARCHITECTURE OF THE RECONFIGURABLE COMPUTING ENGINE FOR DIGITAL SIGNAL PROCESSING APPLICATIONS
         Lien-Fei Chen; National Chung Hsing University
         Yeong-Kang Lai; National Chung Hsing University
 
VLSI-P12.2: APPLICATION-SPECIFIC CONFIGURATION OF MULTITHREADED PROCESSOR ARCHITECTURE FOR EMBEDDED APPLICATIONS
         Mary Kiemb; Seoul National University
         Kiyoung Choi; Seoul National University
 
VLSI-P12.3: RLC EFFECTS ON WORST-CASE SWITCHING PATTERN FOR ON-CHIP BUSES
         Shang-Wei Tu; National Chiao Tung University
         Jing-Yang Jou; National Chiao Tung University
         Yao-Wen Chang; National Taiwan University
 
VLSI-P12.4: FAST RECONFIGURING MESH-CONNECTED VLSI ARRAYS
         Jigang Wu; Nanyang Technological University
         Thambipillai Srikanthan; Nanyang Technological University
 

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