VLSI-P7: Arithmetic and Cryptography

Session Type: Poster
Time: Tuesday, May 25, 14:15 - 15:45
Location: Poster Area 3
Chair: Jerry Jou, National Central University, Taiwan
 
VLSI-P7.1: A NOVEL RADIX-4 BIT-LEVEL MODULAR MULTIPLIER FOR FAST RSA CRYPTOSYSTEM
         Jin-Hua Hong; National University of Kaohsiung
         Bin-Yan Tsai; National University of Kaohsiung
         Liang-Te Lu; National University of Kaohsiung
         Shao-Hui Shieh; National Tsing-Hua University
 
VLSI-P7.2: DESIGN OF RESIDUE-TO-BINARY CONVERTER FOR A NEW 5-MODULI SUPERSET RESIDUE NUMBER SYSTEM
         Bin Cao; Nanyang Technological University
         Thambipillai Srikanthan; Nanyang Technological University
         Chip-Hong Chang; Nanyang Technological University
 
VLSI-P7.3: AN ERROR PATTERN ROM COMPRESSION METHOD FOR CONTINUOUS DATA
         Byung-Do Yang; KAIST
         Lee-Sup Kim; KAIST
 
VLSI-P7.4: GF(2K) MULTIPLIERS BASED ON MONTGOMERY MULTIPLICATION ALGORITHM
         Apostolos Fournaris; University of Patras
         Odysseas Koufopavlou; University of Patras
 
VLSI-P7.5: LOGICALLY REVERSIBLE ARITHMETIC CIRCUIT USING PASS-TRANSISTOR
         Takashi Hisakado; Kyoto University
         Hiroyoshi Iketo; Kyoto University
         Kohshi Okumura; Kyoto University
 

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