VLSI-P6: Arithmetic and DSP Implementation

Session Type: Poster
Time: Tuesday, May 25, 14:15 - 15:45
Location: Poster Area 10
Chair: Jerry Jou, National Central University, Taiwan
 
VLSI-P6.1: VLSI-EFFICIENT IMPLEMENTATION OF FULL ADDER-BASED MEDIAN FILTER
         Adrian Burian; Tampere University of Technology
         Jarmo Takala; Tampere University of Technology
 
VLSI-P6.2: STATIC FLOATING-POINT UNIT WITH IMPLICIT EXPONENT TRACKING FOR EMBEDDED DSP
         Hung-Yueh Lin; National Chiao Tung University
         Tay-Jyi Lin; National Chiao Tung University
         Chie-Min Chao; National Chiao Tung University
         Yen-Chin Liao; National Chiao Tung University
         Chih-Wei Liu; National Chiao Tung University
         Chein-Wei Jen; National Chiao Tung University
 
VLSI-P6.3: SAMPLED ANALOG ARCHITECTURE FOR DCT AND DST
         Ashis Kumar Mal; Indian Institute of Technology, Kharagpur
         Arindam Basu; Indian Institute of Technology, Kharagpur
         Anindya Sundar Dhar; Indian Institute of Technology, Kharagpur
 
VLSI-P6.4: B-SPLINE FACTORIZATION-BASED ARCHITECTURE FOR INVERSE DISCRETE WAVELET TRANSFORM
         Chao-Tsung Huang; National Taiwan University
         Po-Chih Tseng; National Taiwan University
         Liang-Gee Chen; National Taiwan University
 
VLSI-P6.5: DESIGN OF AN EFFICIENT VARIABLE-LENGTH FFT PROCESSOR
         Chung-Ping Hung; National Chiao Tung University
         Sau-Gee Chen; National Chiao Tung University
         Kun-Lung Chen; National Chiao Tung University
 

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