VLSI-P9: FPGA and PLA

Session Type: Poster
Time: Wednesday, May 26, 09:30 - 11:00
Location: Poster Area 8
Chair: John Lach, University of Virginia
 
VLSI-P9.1: A NOVEL SCHEME OF IMPLEMENTING HIGH SPEED AWGN COMMUNICATION CHANNEL EMULATORS IN FPGAS
         Yongquan Fan; McGill University
         Zeljko Zilic; McGill University
 
VLSI-P9.2: A HIGH PERFORMANCE LOW POWER DYNAMIC PLA WITH CONDITIONAL EVALUATION SCHEME
         Kwang-Il Oh; KAIST
         Lee-Sup Kim; KAIST
 
VLSI-P9.3: AN EMBEDDED FLEXIBLE CONTENT-ADDRESSABLE MEMORY CORE FOR INCLUSION IN A FIELD-PROGRAMMABLE GATE ARRAY
         Steven J.E. Wilton; University of British Columbia
         Christopher W. Jones; Greenville, SC
         Julien Lamoureux; University of British Columbia
 
VLSI-P9.4: A UNIFIED ARCHITECTURE OF MD5 AND RIPEMD-160 HASH ALGORITHMS
         Chiu-Wah Ng; University of Hong Kong
         Tung-Sang Ng; University of Hong Kong
         Kun-Wah Yip; University of Hong Kong
 
VLSI-P9.5: WHIRLPOOL HASH FUNCTION: ARCHITECTURE AND VLSI IMPLEMENTATION
         Paris Kitsos; University of Patras
         Odysseas Koufopavlou; University of Patras
 

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