VLSI-P4: Arithmetic Module Implementation

Session Type: Poster
Time: Tuesday, May 25, 09:30 - 11:00
Location: Poster Area 10
Chair: Jerry Jou, National Central University, Taiwan
 
VLSI-P4.1: A LOW-POWER 1.85 GHZ 32-BIT CARRY LOOKAHEAD ADDER USING DUAL PATH ALL-N-LOGIC
         Ge Yang; University of California, Santa Cruz
         Seong-Ook Jung; T-RAM
         Kwang-Hyun Baek; Rockwell Scientific
         Soo Hwan Kim; Korea University
         Suki Kim; Korea University
         Sung-Mo Kang; University of California, Santa Cruz
 
VLSI-P4.2: GIGAHERTZ-RANGE MCML MULTIPLIER ARCHITECTURES
         Venkat Srinivasan; Virginia Tech
         Dong Ha; Virginia Tech
         Jos Sulistyo; Virginia Tech
 
VLSI-P4.3: A PROGRAMMABLE BASE 2D-LNS MAC WITH SELF-GENERATED LOOK-UP TABLES
         Wenjing Zhang; University of Calgary
         Graham Jullien; University of Calgary
         Vassil Dimitrov; University of Calgary
 
VLSI-P4.4: A DESIGN OF 4-OPERAND REDUNDANT BINARY PARALLEL ADDER USING NEURON MOS
         Masahiro Sakamoto; Hiroshima City University
         Shuusaku Mizukami; Hiroshima City University
         Daisuke Hamano; Hiroshima City University
         Hisato Fujisaka; Hiroshima City University
 
VLSI-P4.5: A LOW POWER HIGH SPEED ACCUMULATOR FOR DDFS APPLICATIONS
         Michael Chappell; Oxford University
         Alistair McEwan; Oxford University
 

Home -||- Technical Program -||- Call for Participation -||- Paper Submission -||- Paper Review -||- Plenaries
Invited Sessions -||- Registration -||- Tutorials/Short Courses -||- Forums -||- Technical Program Committee
MySchedule -||- Exhibits -||- Housing -||- Information -||- Committee -||- Contact Us

©2021 Conference Management Services -||- email: organizers@iscas2004.org -||- Last updated Friday, August 17, 2012