VLSI-L17: I/O Circuits

Session Type: Lecture
Time: Wednesday, May 26, 09:30 - 11:00
Location: Junior Ballroom A/B
Co-Chairs: Mohamad Sawan, Ecole Polytechnique de Montreal and Radu M. Secareanu, Motorola, Inc.
 
VLSI-L17.1: LOW COMPLEXITY DIGITAL PLL FOR INSTANT ACQUISITION CDR
         Gordon Allan; Carleton University
         John Knight; Carleton University
 
VLSI-L17.2: A TECHNIQUE TO DESKEW DIFFERENTIAL PCB TRACES
         Amer Atrash; Georgia Institute of Technology
         Brian Butka; Integrated Device Technologies
 
VLSI-L17.3: A NEW INTERPOLATED SYMBOL TIMING RECOVERY METHOD
         Xiong Liu; University of California, Los Angeles
         Alan N. Willson, Jr.; University of California, Los Angeles
 
VLSI-L17.4: A NEW SCHMITT TRIGGER CIRCUIT IN A 0.13 UM 1/2.5 V CMOS PROCESS TO RECEIVE 3.3 V INPUT SIGNALS
         Shih-Lun Chen; National Chiao Tung University
         Ming-Dou Ker; National Chiao Tung University
 
VLSI-L17.5: DESIGN ON MIXED-VOLTAGE-TOLERANT I/O INTERFACE WITH NOVEL TRACKING CIRCUITS IN A 0.13-ΜM CMOS TECHNOLOGY
         Che-Hao Chuang; Industrial Technology Research Institute
         Ming-Dou Ker; National Chiao Tung University
 

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