VLSI-L14: Turbo and Viterbi Algorithms

Session Type: Lecture
Time: Tuesday, May 25, 14:15 - 15:45
Location: Junior Ballroom C
Co-Chairs: An-Yeu Wu, National Taiwan University and Thanos Stouraitis, University of Patras
 
VLSI-L14.1: NOVEL PIPELINING OF MSB-FIRST ADD-COMPARE SELECT UNIT STRUCTURE FOR VITERBI DECODERS
         Keshab K. Parhi; University of Minnesota
 
VLSI-L14.2: PIPELINED PARALLEL ARCHITECTURE FOR HIGH THROUGHPUT MAP DETECTORS
         Ruwan Ratnayake; Harvard University
         Gu-Yeon Wei; Harvard University
         Aleksandar Kavcic; Harvard University
 
VLSI-L14.3: PARALLEL TURBO DECODING
         Yuping Zhang; University of Minnesota
         Keshab K. Parhi; University of Minnesota
 
VLSI-L14.4: VLSI ARCHITECTURE EXPLORATION FOR SLIDING-WINDOW LOG-MAP DECODERS
         Chien-Ming Wu; Chip Implementation Center (CIC)
         Ming-Der Shieh; National Cheng Kung University
         Chien-Hsing Wu; National Chung Cheng University
         Ying-Tsung Hwang; National Yunlin University of Science and Technology
         Jun-Hong Chen; National Cheng King University
         Hsin-Fu Lo; Chip Implementation Center (CIC)
 
VLSI-L14.5: AN ASYNCHRONOUS SOVA DECODER FOR WIRELESS COMMUNICATION APPLICATION
         Wing-Kin Chan; The Chinese University of Hong Kong
         Chiu-Sing Choy; The Chinese University of Hong Kong
         Cheong-Fat Chan; The Chinese University of Hong Kong
         Kong-Pang Pun; The Chinese University of Hong Kong
 

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