VLSI-L1: Low Power Circuits and Architecture

Session Type: Lecture
Time: Monday, May 24, 09:30 - 11:00
Location: Junior Ballroom A/B
Co-Chairs: Bin-Da Liu, National Cheng Kung University and Mircea R. Stan, University of Virginia
 
VLSI-L1.1: TRANSFERRING PERFORMANCE GAIN FROM SOFTWARE PREFETCHING TO ENERGY REDUCTION
         Deepak Agarwal; AMD
         Sumitkumar Pamnani; AMD
         Gang Qu; University of Maryland, College Park
         Donald Yeung; University of Maryland, College Park
 
VLSI-L1.2: A LOW-POWER DECIMATION FILTER FOR A SIGMA-DELTA CONVERTER BASED ON A POWER-OPTMIZED SINC FILTER
         Andrea Gerosa; University of Padova
         Andrea Neviani; University of Padova
 
VLSI-L1.3: EMPIRICAL EVALUATION OF TIMING AND POWER IN RESONANT CLOCK DISTRIBUTION
         Juang-ying Chueh; University of Michigan
         Conrad Ziesler; University of Michigan
         Marios Papaefthymiou; University of Michigan
 
VLSI-L1.4: A POWER AND AREA EFFICIENT MULTI-MODE FEC PROCESSOR
         Yi-Chen Tseng; National Chiao Tung University
         Chien-Ching Lin; National Chiao Tung University
         Hsie-Chia Chang; National Chiao Tung University
         Chen-Yi Lee; National Chiao Tung University
 
VLSI-L1.5: ASYNCHRONOUS, QUASI-ADIABATIC (ASYNCHROBATIC) LOGIC FOR LOW-POWER VERY WIDE DATA WIDTH APPLICATIONS
         David J. Willingham; University of Westminster
         Izzet Kale; University of Westminster
 

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