VLSI-L10: Arithmetic

Session Type: Lecture
Time: Tuesday, May 25, 09:30 - 11:00
Location: Junior Ballroom C
Co-Chairs: Thanos Stouraitis, University of Patras and Jing-Yang Jou, National Chiao Tung University
 
VLSI-L10.1: A SCALABLE COMPACT ARCHITECTURE FOR THE COMPUTATION OF INTEGER BINARY LOGARITHMS THROUGH LINEAR APPROXIMATION
         Christophe Layer; University of Ulm
         Hans-Jörg Pfleiderer; University of Ulm
         Christoph Heer; Infineon Technologies AG
 
VLSI-L10.2: A METHOD FOR INCREASING THE THROUGHPUT OF FIXED COEFFICIENT DIGIT-SERIAL/PARALLEL MULTIPLIERS
         Magnus Karlsson; University of Kalmar
         Mark Vesterbacka; Linköping University
         Wlodek Kulesza; University of Kalmar
 
VLSI-L10.3: MODULO DEFLATION IN (2N +1, 2N, 2N -1) CONVERTERS
         Shaoqiang Bi; Concordia University
         Wei Wang; University of Western Ontario
         Asim Al-Khalili; Concordia University
 
VLSI-L10.4: GEOMETRIC-MEAN INTERPOLATION FOR LOGARITHMIC NUMBER SYSTEMS
         Mark Arnold; Lehigh University
 
VLSI-L10.5: A LOW POWER 16-BIT BOOTH LEAPFROG ARRAY MULTIPLIER USING DYNAMIC ADDERS
         Kwen-Siong Chong; Nanyang Technological University
         Bah-Hwee Gwee; Nanyang Technological University
         Joseph Sylvester Chang; Nanyang Technological University
 

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