VLSI-L3: Low Power Arithmetic

Session Type: Lecture
Time: Monday, May 24, 11:15 - 12:45
Location: Junior Ballroom A/B
Co-Chairs: Robert C. Chang, National Chung Hsin University and Mircea R. Stan, University of Virginia
 
VLSI-L3.1: GLITCH-CONSCIOUS LOW-POWER DESIGN OF ARITHMETIC CIRCUITS
         Henrik Eriksson; Chalmers University of Technology
         Per Larsson-Edefors; Chalmers University of Technology
 
VLSI-L3.2: REDUCING MULTIPLIER ENERGY BY DATA-DRIVEN VOLTAGE VARIATION
         Tomoyuki Yamanaka; Fukuoka University
         Vasily Moshnyaga; Fukuoka University
 
VLSI-L3.3: A NOVEL FAST LOW VOLTAGE DYNAMIC THRESHOLD TRUE SINGLE PHASE CLOCKING ADIABATIC CIRCUIT
         Michael Yang; University of Waterloo
         James Barby; University of Waterloo
 
VLSI-L3.4: A LOW POWER AND FAST WAKE UP CIRCUIT
         Hung-wei Chen; National United University
         Wen-Cheng Yen; Faraday Technology Corporation
 
VLSI-L3.5: A LEAKAGE ESTIMATION AND REDUCTION TECHNIQUE FOR SCALED CMOS LOGIC CIRCUITS CONSIDERING GATE-LEAKAGE
         Hafijur Rahman; Arizona State University
         Chaitali Chakrabarti; Arizona State University
 

Home -||- Technical Program -||- Call for Participation -||- Paper Submission -||- Paper Review -||- Plenaries
Invited Sessions -||- Registration -||- Tutorials/Short Courses -||- Forums -||- Technical Program Committee
MySchedule -||- Exhibits -||- Housing -||- Information -||- Committee -||- Contact Us

©2021 Conference Management Services -||- email: organizers@iscas2004.org -||- Last updated Friday, August 17, 2012