VLSI-L8: Coding

Session Type: Lecture
Time: Monday, May 24, 16:00 - 17:30
Location: Junior Ballroom C
Co-Chairs: Dimitrios Soudris, Democritus University of Trace and Malgorzata Chrzanowska-Jeske, Portland State University
 
VLSI-L8.1: A FAST REED-SOLOMON PRODUCT-CODE DECODER WITHOUT REDUNDANT COMPUTATIONS
         Hyun-Yong Lee; KAIST
         In-Cheol Park; KAIST
 
VLSI-L8.2: NOVEL BIT MANIPULATION UNIT FOR COMMUNICATION DIGITAL SIGNAL PROCESSORS
         Sung Dae Kim; Ajou university
         Sug Hyun Jeong; Ajou university
         Myung Hoon Sunwoo; Ajou university
         Kyung Ho Kim; Samsung Electronics
 
VLSI-L8.3: JOINT CODE-ENCODER-DECODER DESIGN FOR LDPC CODING SYSTEM VLSI IMPLEMENTATION
         Hao Zhong; Rensselaer Polytechnic Institute
         Tong Zhang; Rensselaer Polytechnic Institute
 
VLSI-L8.4: MULTI-LEVEL MEMORY SYSTEMS USING ERROR CONTROL CODES
         Hsie-Chia Chang; National Chiao Tung University
         Chien-Ching Lin; National Chiao Tung University
         Tien-Yuan Hsiao; National Chiao Tung University
         Jieh-Tsorng Wu; National Chiao Tung University
         Ta-Hui Wang; National Chiao Tung University
 
VLSI-L8.5: MEMORY-BASED LOW DENSITY PARITY CHECK CODE DECODER ARCHITECTURE USING LOOSELY COUPLED TWO DATA-FLOWS
         Se-Hyeon Kang; KAIST
         In-Cheol Park; KAIST
 

Home -||- Technical Program -||- Call for Participation -||- Paper Submission -||- Paper Review -||- Plenaries
Invited Sessions -||- Registration -||- Tutorials/Short Courses -||- Forums -||- Technical Program Committee
MySchedule -||- Exhibits -||- Housing -||- Information -||- Committee -||- Contact Us

©2021 Conference Management Services -||- email: organizers@iscas2004.org -||- Last updated Friday, August 17, 2012