CAD-P2: CAD for Digital Circuits

Session Type: Poster
Time: Monday, May 24, 11:15 - 12:45
Location: Poster Area 2
Chair: Sung Kyu Lim, Georgia Institute of Technology
 
CAD-P2.1: A DESIGN FLOW FOR MULTIPLIERLESS LINEAR-PHASE FIR FILTERS: FROM SYSTEM SPECIFICATION TO VERILOG CODE
         Kai-Yuan Jheng; National Taiwan University
         Shyh-Jye Jou; National Central University
         An-Yeu (Andy) Wu; National Taiwan University
 
CAD-P2.2: SHIELDING AREA OPTIMIZATION UNDER THE SOLUTION OF INTERCONNECT CROSSTALK
         Xin Zhao; Tsinghua University
         Yici Cai; Tsinghua University
         Qiang Zhou; Tsinghua University
         Xianlong Hong; Tsinghua University
         Lei He; University of California, Los Angeles
         Jinjun Xiong; University of California, Los Angeles
 
CAD-P2.3: PERFORMANCE METRICS FOR ASYNCHRONOUS DIGITAL CIRCUITS APPLICABLE TO COMPUTER-AIDED DESIGN
         Rajani Parthasarthy; University of Pittsburgh
         Ivan Kourtev; University of Pittsburgh
 
CAD-P2.4: RTL/ISS CO-MODELING METHODOLOGY FOR EMBEDDED PROCESSOR USING SYSTEMC
         Yoichi Yuyama; Kyoto University
         Masao Aramoto; Kyoto University
         Kazutoshi Kobayashi; University of Tokyo
         Hidetoshi Onodera; Kyoto University
 

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