CAD-L7: Interconnect and Clock Distribution

Session Type: Lecture
Time: Tuesday, May 25, 14:15 - 15:45
Location: Galiano
Co-Chairs: Alan Mantooth, University of Arkansas and Sung Kyu Lim, Georgia Institute of Technology
 
CAD-L7.1: PARTIAL RANDOM WALK FOR LARGE LINEAR NETWORK ANALYSIS
         Weikun Guo; University of California, Riverside
         Sheldon Tan; University of California, Riverside
         Zuying Luo; Tsinghua University
         Xianlong Hong; Tsinghua University
 
CAD-L7.2: MATRIX PENCIL BASED REALIZABLE REDUCTION FOR DISTRIBUTED INTERCONNECTS
         Janet Meiling Wang; University of Arizona
         Omar Hafiz; University of Arizona
 
CAD-L7.3: FREQUENCY DRIVEN REPEATER INSERTION FOR DEEP SUBMICRON
         Nisar Ahmed; University of Texas, Dallas
         Mohammad Tehranipour; University of Texas, Dallas
         Dian Zhou; University of Texas, Dallas
         Mehrdad Nourani; University of Texas, Dallas
 
CAD-L7.4: MODELING AND IMPLEMENTATION OF TWISTED DIFFERENTIAL ON-CHIP INTERCONNECTS FOR CROSSTALK NOISE REDUCTION
         Ilhan Hatirnaz; Swiss Federal Institute of Technology (EPFL)
         Yusuf Leblebici; Swiss Federal Institute of Technology (EPFL)
 
CAD-L7.5: DELAY BOUND BASED CMOS GATE SIZING TECHNIQUE
         Alexandre Verle; Université de Montpellier II
         Xavier Michel; Université de Montpellier II
         Philippe Maurine; Université de Montpellier II
         Nadine Azémard; Université de Montpellier II
         Daniel Auvergne; Université de Montpellier II
 

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