CAD-L2: Placement and Routing II

Session Type: Lecture
Time: Monday, May 24, 11:15 - 12:45
Location: Galiano
Co-Chairs: Yoji Kajitani, University of Kitakyushu and Sung Kyu Lim, Georgia Institute of Technology
 
CAD-L2.1: ROUTING RESOURCES CONSUMPTION ON M-ARCH AND X-ARCH
         Bo-Kyung Choi; University of California, Los Angeles
         Charles Chiang; Synopsys, Inc.
         Jamil Kawa; Synopsys, Inc.
         Majid Sarrafzadeh; University of California, Los Angeles
 
CAD-L2.2: A PLACEMENT ALGORITHM FOR IMPLEMENTATION OF ANALOG LSI/VLSI SYSTEMS
         Lihong Zhang; Concordia University
         Rabindra Raut; Concordia University
         Yingtao Jiang; University of Nevada
 
CAD-L2.3: RECURSIVELY COMBINE FLOORPLAN AND Q-PLACE IN MIXED MODE PLACEMENT BASED ON CIRCUIT'S VARIETY OF BLOCK CONFIGURATION
         Changqi Yang; Tsinghua University
         Xianlong Hong; Tsinghua University
         Hannah Honghua Yang; Intel Corporation
         Qiang Zhou; Tsinghua University
         Yici Cai; Tsinghua University
         Yongqiang Lu; Tsinghua University
 
CAD-L2.4: LAYER ASSIGNMENT ALGORITHM FOR RLC CROSSTALK MINIMIZATION
         Bin Liu; Tsinghua University
         Yici Cai; Tsinghua University
         Qiang Zhou; Tsinghua University
         Xianlong Hong; Tsinghua University
 
CAD-L2.5: CROSSTALK DRIVEN ROUTING RESOURCE ASSIGNMENT
         Hailong Yao; Tsinghua University
         Qiang Zhou; Tsinghua University
         Xianlong Hong; Tsinghua University
         Yici Cai; Tsinghua University
 

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