ASP-P10: Mixed Signal and Sensor Interface Circuits

Session Type: Poster
Time: Tuesday, May 25, 11:15 - 12:45
Location: Poster Area 8
Chair: Ralph Etienne-Cummings, Johns Hopkins University
 
ASP-P10.1: AN INTEGRATED A-SI TFT DEMULTIPLEXER FOR DRIVING GATE LINES IN ACTIVE-MATRIX ARRAYS
         Kambiz Moez; University of Waterloo
 
ASP-P10.2: ON-CHIP CALIBRATION TECHNIQUE FOR DELAY LINE BASED BIST JITTER MEASUREMENT
         Bryan Nelson; University of Washington
         Mani Soma; University of Washington
 
ASP-P10.3: A SINGLE-ENDED TO DIFFERENTIAL CAPACITIVE SENSOR INTERFACE CIRCUIT DESIGNED IN CMOS TECHNOLOGY
         Tajeshwar Singh; Norwegian University of Science and Technology
         Trond Ytterdal; Norwegian University of Science and Technology
 
ASP-P10.4: 4/2 PAM SERIAL LINK TRANSMITTER WITH TUNABLE PRE-EMPHASIS
         Chih-Hsien Lin; National Central University
         Chang-Hsiao Tsai; National Central University
         Chih-Ning Chen; National Central University
         Shyh-Jye Jou; National Central University
 

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