| Paper ID | SS-8.6 |
| Paper Title |
HARDWARE IMPLEMENTATION OF ITERATIVE PROJECTION-AGGREGATION DECODING OF REED-MULLER CODES |
| Authors |
Marzieh Hashemipour-Nazari, Kees Goossens, Alexios Balatsoukas-Stimming, Eindhoven University of Technology, Netherlands |
| Session | SS-8: Near-ML Decoding of Error-correcting Codes: Algorithms and Implementation |
| Location | Gather.Town |
| Session Time: | Wednesday, 09 June, 16:30 - 17:15 |
| Presentation Time: | Wednesday, 09 June, 16:30 - 17:15 |
| Presentation |
Poster
|
| Topic |
Special Sessions: Near-ML Decoding of Error-correcting Codes: Algorithms and Implementation |
| IEEE Xplore Open Preview |
Click here to view in IEEE Xplore |
| Virtual Presentation |
Click here to watch in the Virtual Conference |
| Abstract |
In this work, we present a simplification and a corresponding hardware architecture for hard-decision recursive projection-aggregation (RPA) decoding of Reed-Muller (RM) codes. In particular, we transform the recursive structure of RPA decoding into a simpler and iterative structure with minimal error-correction degradation. Our simulation results for RM(7,3) show that the proposed simplification has a small error-correcting performance degradation (0.005 in terms of channel crossover probability) while reducing the average number of computations by up to 40%. In addition, we describe the first fully parallel hardware architecture for simplified RPA decoding. We present FPGA implementation results for an RM(6,3) code on a Xilinx Virtex-7 FPGA showing that our proposed architecture achieves a throughput of 171 Mbps at a frequency of 80 MHz |
