| Paper ID | SS-8.5 |
| Paper Title |
HIGH-THROUGHPUT VLSI ARCHITECTURE FOR SOFT-DECISION DECODING WITH ORBGRAND |
| Authors |
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren Gross, McGill University, Canada |
| Session | SS-8: Near-ML Decoding of Error-correcting Codes: Algorithms and Implementation |
| Location | Gather.Town |
| Session Time: | Wednesday, 09 June, 16:30 - 17:15 |
| Presentation Time: | Wednesday, 09 June, 16:30 - 17:15 |
| Presentation |
Poster
|
| Topic |
Special Sessions: Near-ML Decoding of Error-correcting Codes: Algorithms and Implementation |
| IEEE Xplore Open Preview |
Click here to view in IEEE Xplore |
| Virtual Presentation |
Click here to watch in the Virtual Conference |
| Abstract |
Guessing Random Additive Noise Decoding (GRAND) is a recently proposed approximate Maximum Likelihood (ML) decoding technique that can decode any linear error-correcting block code. Ordered Reliability Bits GRAND (ORBGRAND) is a powerful variant of GRAND, which outperforms the original GRAND technique by generating error patterns in a specific order. Moreover, their simplicity at the algorithm level renders GRAND family a desirable candidate for applications that demand very high throughput. This work reports the first-ever hardware architecture for ORBGRAND, which achieves an average throughput of up to 42.5 Gbps for a code length of 128 at an SNR of 10 dB. Moreover, the proposed hardware can be used to decode any code provided the length and rate constraints. Compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar (128, 105) code, the proposed VLSI implementation has 49X more average throughput while maintaining similar decoding performance. |
