| Paper ID | ASPS-1.2 |
| Paper Title |
SCALED FAST NESTED KEY EQUATION SOLVER FOR GENERALIZED INTEGRATED INTERLEAVED BCH DECODERS |
| Authors |
Zhenshan Xie, Xinmiao Zhang, The Ohio State University, United States |
| Session | ASPS-1: Architectures |
| Location | Gather.Town |
| Session Time: | Tuesday, 08 June, 16:30 - 17:15 |
| Presentation Time: | Tuesday, 08 June, 16:30 - 17:15 |
| Presentation |
Poster
|
| Topic |
Applied Signal Processing Systems: Design & Synthesis [DIS-ARCH, DIS-LPWR] |
| IEEE Xplore Open Preview |
Click here to view in IEEE Xplore |
| Virtual Presentation |
Click here to watch in the Virtual Conference |
| Abstract |
The generalized integrated interleaved BCH (GII-BCH) codes are among the best error-correcting codes for next-generation terabit/s memories. The key equation solver (KES) in the nested decoding of GII codes limits the achievable clock frequency. Recently, by polynomial scalar pre-computation, the critical path of the nested KES for Reed-Solomon (RS)-based GII codes has been reduced to one multiplier. However, for GII-BCH codes, the nested KES has more complicated formulas in order to skip the odd iterations and hence prior techniques do not directly extend. This paper proposes novel reformulations of the nested BCH KES to enable scalar pre-computation. Additionally, polynomial scaling is incorporated to enable complexity reduction. As a result, the critical path of the nested BCH KES with odd iterations skipped is reduced to one multiplier. For an example GII-BCH code over GF(2^12), the proposed design reduces the average nested BCH KES latency to around a half with similar silicon area compared to the best prior design. |
