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My Asilomar 2019 Schedule

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Technical Program

Paper Detail

Paper:TP8b1-1
Session:Architectures for Arithmetic and Signal Processing Systems
Session Time:Tuesday, November 5, 15:30 - 17:35
Presentation Time:Tuesday, November 5, 15:30 - 17:35
Presentation: Poster
Topic: Architectures and Implementation: Arithmetic and Algorithms
Paper Title: FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic Through Primitive Instantiation
Authors: Ayan Palchaudhuri; Indian Institute of Technology Kharagpur 
 Anindya Sundar Dhar; Indian Institute of Technology Kharagpur